As a semiconductor memory device gets integrated further and further, internal voltages of various voltage levels are used inside the memory such that a separate voltage is used for a core region or a higher voltage is used for over-driving operation of high speed data access, in order to reduce power consumption. A reference voltage generating circuit is to output a reference voltage for generating multi-level internal voltages for use in the memory device.
Typically, a supply voltage that is supplied from outside to the memory device include variation in its voltage level. A band gap reference circuit is used to output a voltage that keeps a constant level even if it happens variation in the supply voltage. The reference voltage generating circuit uses the output voltage that is outputted from the band gap reference circuit to generate the voltage that is referenced to produce the internal voltages that are needed for the internal operations.
FIG. 1 provides a block diagram for generating an internal voltage in a typical memory device.
Referring to FIG. 1, for generating the internal voltages in the memory device, there is included a band gap reference circuit 10, a reference voltage generating circuit 20, a reference voltage adjusting fuse unit 40 and an internal voltage supplying unit 30.
The band gap reference circuit 10 receives an external voltage VDD to output a band gap reference voltage Vbg of a constant level regardless of variation of the external voltage VDD. The reference voltage generating circuit 20 uses the band gap reference voltage Vbg that is outputted from the band gap reference circuit 10 to generate a reference voltage Vref having a predetermined level. The reference voltage adjusting fuse unit 40 adjusts the voltage level of the reference voltage Vref that is outputted from the reference voltage generating circuit 20. The internal voltage supplying unit 30 receives the reference voltage Vref from the reference voltage generating circuit 20 to generate various internal voltages Vcore, Vperi, Vpp, Vbb for use in the operation of the memory device.
Here, ‘Vcore’ is an internal voltage for use in the core region having unit cells in the memory device, ‘Vperi’ is an internal voltage for use in the peripheral region from the core region in the memory device, ‘Vpp’ is an internal voltage that is used when a higher voltage is needed for over-driving operation, and ‘Vbb’ is an internal voltage of a lower level than a ground voltage VSS, which is used as a board bias supply voltage in the core region.
FIG. 2 is a circuit diagram of the reference voltage generating circuit 20 and the reference voltage adjusting fuse unit 40 in FIG. 1.
Referring to FIG. 2, the reference voltage adjusting fuse unit 40 includes a fuse box 41 and a fuse decoder 42. The fuse box 41 has a number of fuses and outputs control codes F0-F2, F0b-F2b that are coded by selective short of the fuses. The fuse decoder 41 decodes the control codes F0-F2, F0b-F2b to output decoded signals TRIM0-TRIM7.
The reference generating circuit 20 includes a variable resistor unit 22 and an operational amplifier 21. The variable resistor unit 22 varies its resistance in response to the decoded signals TRIM0-TRIM7 that are outputted from the fuse decoder 41. The operational amplifier 21 receives the band gap reference voltage Vbg as its positive input to output the reference voltage Vref.
The variable resistor unit 22 has a resistor R1, a number of resistors R2_1-R2_8, and a number of switching MOS transistors MN1-MN11. One end of the resistor R1 is coupled to the output of the operational amplifier 21 that outputs the reference voltage Vref based on the decoded signals TRIM0-TRIM7. The resistors R2_1-R2_8 are serially coupled between the other end of the resistor R1 and the ground voltage VSS. The switching MOS transistors MN1-MN11 connect a node x to one end of the selected one of the resistors R2_1-R2_8 based on the decoded signals TRIM0-TRIM7.
The operational amplifier 20 includes a diode-coupled MOS transistor MP2, a PMOS transistor MP1, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3 and a PMOS transistor MP3. The diode-coupled MOS transistor MP2 has one end that is coupled to the supply voltage VDD, and a gate that is coupled to the other end of the MOS transistor MP2. The PMOS transistor MP1 has one end that is coupled to the supply voltage VDD, and a gate that is coupled to the gate of the PMOS transistor MP2 to form a current mirror. The NMOS transistor MN1 has one end that is coupled to the other end of the PMOS transistor MP1, and a gate that receives the band gap reference voltage Vbg. The NMOS transistor MN2 has one end that is coupled to the other end of the PMOS transistor MP2 and a gate that receives the voltage Vbg_ref that is inputted to the node x. The NMOS transistor MN3 has one end that is coupled to the other ends of the NMOS transistor MN1, MN2, the other end that is coupled to the ground voltage VSS, and a gate that receives the band gap reference voltage Vbg. And, the PMOS transistor MP3 has one end that is coupled to the supply voltage VDD, a gate that is coupled to the one end of the NMOS transistor MN1, and the other end that outputs the reference voltage Vref.
FIG. 3 describes a circuit diagram of the fuse box 41 in FIG. 2.
Referring to FIG. 3, the fuse box 41 includes 3 fuse sets 41a, 41b, 41c for outputting the 6-bit coded signals F0-F2, F0b-F2b. 
One of the fuse sets 41a includes a PMOS transistor MP4, a fuse f1, a NMOS transistor MN12, and inverters I11, I12, I13. The PMOS transistor MP4 has one end that is coupled to the supply voltage VDD, and a gate that is coupled to the ground voltage to keep a turn-on state. The fuse f1 has one end that is coupled to the other end of the PMOS transistor MP4. The inverter I1 has its input that is coupled to the other end of the fuse f1. The NMOS transistor MN12 connects the other end of the fuse f1 to the ground voltage VSS and has a gate that receives the output of the inverter I1. The inverter I12 inverts the output of the inverter I1 to output the coded signal F0. The inverter I13 inverts the output of the inverter I12 to output the coded signal F0b. Also, the other fuse sets 41b, 41c are constituted as similar to the fuse set 41a so as to output the coded signals F1, F1b and the coded signals F2, F2b, respectively.
FIG. 4 shows a circuit diagram of the fuse decoder 42 in FIG. 2.
Referring to FIG. 4, the fuse decoder 42 includes a number of NAND gates ND1-ND8 for receiving three different signals among the coded signals F0-F2, F0b-F2b that are outputted from the fuse box 41, respectively, and a number of inverters I10-I17 for inverting the outputs of the NAND gates ND1-ND8, respectively, to output the decoded signals TRIM0-TRIM7.
It will be described for the operation of internal voltage generating in the memory device with reference to the FIG. 1 to FIG. 4.
First, the band gap reference circuit 10 receives the supply voltage VDD and ground voltage VSS that are provided from outside and outputs the band gap reference voltage that keeps its level constantly regardless of variation in the voltage level of the external voltage VDD.
Typically, the supply voltage that is provided from outside of the band gap device is unstable to have variation in its voltage level. Therefore, the band gap reference circuit 10 generates the band gap reference voltage Vbg of a constant level regardless of the variation of the voltage level of the external voltage to prevent the voltage level variation of the external voltage from being transferred to the internal circuits.
In turn, the reference voltage generating circuit 20 receives the band gap reference voltage Vbg to output the reference voltage of a predetermined voltage. The internal voltage supplying unit 30 uses the reference voltage Vref to generate the internal voltages Vcore, Vperi, Vpp, Vbb to use in the internal operations in the memory device.
At that time, the reference voltage Vref that is outputted from the reference voltage generating circuit 20 is a trimmed voltage that is trimmed by the decoded signals TRIM0-TRIM7 that are outputted from the reference voltage adjusting fuse unit 40.
The reference voltage Vref from The reference voltage generating circuit 20 is an important signal that is a reference for the internal voltage supplying unit 30 to generate the various internal voltages for use in the internal operations.
However, in actual process, the reference voltage Vref is not generated as having a designed voltage level due to various process variables in most cases.
To solve this problem, the memory device employs the reference voltage adjusting fuse unit 40 having a number of fuses. The decoded signals TRIM0-TRIM7 are generated by selectively making the fuses of the reference voltage adjusting fuse unit 40 short in wafer level and, in turn, the reference voltage generating circuit 20 adjusts the voltage level of the reference voltage Vref in response to the decoded signals TRIM0-TRIM7.
Further, it will be described for the steps of generating the decoded signals TRIM0-TRIM7 in the reference voltage adjusting fuse unit 40.
First, the fuse box 41 includes a number of the fuse sets 41a, 41b, 41c corresponding to the number of bits of the outputted coded signals F0-F2, F0b-F2b. When the reference voltage Vref that is measured at the wafer level is not equal to the desired one, the fuses f1, f2, f3 of the fuse boxes 41 are selectively radiated with a laser to code the coded signals F0-F2, F0b-F2b. The fuse decoder 42 receives the coded signals F0-F2, F0b-F2b to activate one of the 8 decoded signals TRIM0-TRIM7 to a high level.
In turn, one of the switching MOS transistors MN4-MN11 is turned on by the decode signals TRIM0-TRIM7 and, accordingly, one end of one of the serially coupled resistors R2_1-R2_8 is connected to the node x. Depending on the resistor that is connected to the node x among the resistors R2_1-R2_8, the reference voltage Vref is adjusted and outputted.
FIG. 5 represents an equivalent circuit diagram for illustrating the voltage level of the reference voltage Vref that is outputted from the reference voltage generating circuit 20 in FIG. 2.
As shown in FIG. 5, when the operational amplifier 21 receives the band gap reference voltage Vbg to its positive input, resistors Ra, Rb are serially coupled between the output of the operational amplifier 21 and the ground voltage VSS, and the operational amplifier 21 receives the voltage on the node x to its negative input, the voltage level of the reference voltage Vref that is outputted from the output of the operation amplifier 21 becomes Vref=Vbg×(1+Ra/Rb).
Here, the resistances of the resistors Ra, Rb are determined by the decoded signals TRIM0-TRIM7 in the reference generating circuit in FIG. 2. For example, when the decoded signal TRIM3 is activated and inputted, the resistance of the resistor Ra is a sum of R2_1-R2_3 and that of the resistor Rb is a sum of R2_4-R2_8.
By the way, in some semiconductor devices, there happens too large error between the designed reference voltage Vref and the actually outputted reference voltage to trim with only the 8 resistors R2_1-R2_8 shown in FIG. 2. In such a case, more than 8 resistors R2_1-R2_8 should be serially coupled.
In that case, the number of the switching MOS transistors increases depending on the extra serially-coupled resistors. Further, as the number of the decoded signal increases, the fuse decoder 42 and the fuse box 41 for outputting the decoded signals increases so much that the area of the integrated circuit should be increased.
For example, when the designed reference voltage is 1.6V and the voltage that is outputted at a test on the wafer is 1.8V, the number of the required resistors is 20 assuming that the voltage level that can be adjusted by one resistor is 0.01. Accordingly, the fuse decoder and the fuse box get complicated.
Here, if each resistor is chosen to have a lager resistance, the number of the resistors can be reduced but the fuse trimming operation cannot be adjusted finely. For example, when the adjustable voltage of each resistor is raised to 0.4V, 5 resistors are enough for the variable resistor unit but the reference voltage that can be adjusted in the fuse trimming operation is to limited to 1.8, 1.76, 1.72, making fine trimming of the reference voltage impossible.
Because process variables are not likely to be set for a just developed product during the semiconductor development, the range of the voltage trimming is wide. However, once the semiconductor is finally developed, the voltage trimming should be performed finely. Therefore, to let fine trimming whiling keeping some trimming range, the number of the resistors is to increase.